The present invention relates to a configurable cellular array of dynamically configurable logic elements, such arrays being generally known as a field-programmable gate array (FPGA). More particularly, the present invention relates to an FPGA including: first and second basic cells, each having a plurality of logic circuits; and a program element for connecting/disconnecting the first and second basic cells to/from each other responsive to a program externally input and storing thereon the connection or disconnection state between these cells. The present invention also relates to a method for fabricating such an FPGA.
An FPGA includes: a gate array, in which a multiplicity of basic cells, each having a plurality of logic circuits, are arranged to form a regular pattern: and an interconnection area, in which a plurality of interconnection lines are arranged to interconnect the basic cells together. In the FPGA, the connection or disconnection state of a line interconnecting a pair of basic cells is determined by a program element, which is controlled by a program.
Various types of program elements are known in the art. Examples of program elements include non-programmable types like anti-fuses, and programmable types like EEPROMs and EPROMS. Although EEPROMs and EPROMs are programmable a limited number of times (hereinafter, referred to as "programmability-limited program elements"), a program element disclosed in Japanese Laid-Open Publication No. 10-4345 is programmable any arbitrary number of times (hereinafter, referred to as "programmability-unlimited program elements"). The program element disclosed in this document includes: an SRAM; and a nonvolatile ROM for storing thereon logic synthesis data.
The non-programmable program elements and programmability-limited program elements can advantageously retain logic synthesis data even after the power has been turned OFF. But the program elements of these types are programmable just a limited number of times. In addition, although these program elements require the application of a high voltage to write data thereon, the resulting write speed is low. For example, a data write speed enabled by an EEPROM or EPROM is on the order of several milliseconds.
On the other hand, the program elements of the type disclosed in Japanese Laid-Open Publication No. 10-4345 are programmable an arbitrary number of times and data can be written thereon at a high speed, because the data stored on a ROM is written onto an SRAM. However, since the program element of this type uses the SRAM, data should be read out from the ROM every time the power is turned ON. Moreover, it is impossible to write logic synthesis data, other than the counterpart written on the ROM, onto the SRAM.